1. Field of the Invention
This invention relates to field-effect transistor having T-shaped gate electrodes.
2. Description of Related Art
The ever smaller dimensions of FET devices have led to the employment of T-shaped gate electrodes. State of the art MOS transistors are fabricated by depositing the gate stack material over the gate oxide and substrate. Lithography and etching processes are used to define the polysilicon gate structures. Next the gate structure and silicon substrate are thermally oxidized. After this, source/drain extensions are implanted. Sometimes the implant is performed using a spacer to create a specific distance between the gate and the as implanted junction. In some instances the S/D extensions for the NFET device will be implanted with no spacer and the PFET S/D extensions will be implanted with a spacer present. A thicker spacer is typically formed after the S/D extensions have been implanted. The deep S/D implants are then performed with the thick spacer present. High temperature anneals are done to activate the junctions after which the S/D and silicides are formed on the top surface of the gate electrode.
Generational improvements for high performance CMOS are obtained by decreasing the transistor line width (L poly), reducing the gate oxide thickness, and decreasing the S/D extension resistance. Smaller L poly results in less distance between source and drain. This results in faster switching speeds for CMOS circuits. However as the L poly gets smaller, the overall area available for silicidation is reduced. This means that as L poly shrinks, line resistance is increased. Increased line resistance causes degradation in device performance.
Drive currents for MOS devices are inversely proportional to gate oxide thicknesses. Thinner gate oxides yield higher drive currents. One problem with this is that as the gate oxide is thinned, polysilicon depletion effects become more pronounced. Polysilicon depletion is an effective thickening of the gate oxide.
One method of minimizing this problem is to employ gate predoping. In this technique the blanket polysilicon-Si is implanted prior to gate patterning. The problem with the predoping method is that etching and gate profiles are difficult to control.
S/D extension resistance is another important performance factor. Drive currents can be increased by reducing S/D extension resistance. Increasing the S/D extension dose leads to lower resistance but has the unwanted side effect of increasing the junction depth. One method for overcoming this problem is to implant the extension first with no spacer present and then form a thin spacer and perform a second implant. Alternatively, a notched gate may be used to perform this task by implanting at two or more angles. The drawback to the first method is increased process complexity, while the drawback to the second method is that notched gates typically have reduced line width control.
U.S. Pat. No. 4,679,311 of Lakhani et al. entitled xe2x80x9cMethod for Fabricating Self-Aligned Field-Effect Transistor Having T-Shaped Gate Electrode, Sub-Micron Gate Length and Variable Drain to Gate Spacingxe2x80x9d relates to a dual gate MESFET (Metal Semiconductor Field Effect Transistor) formed on a compound semiconductor substrate composed of a material such as GaAs, InP, GaAlAs, etc. Lakhani et al. teaches a method of creating a xe2x80x9cTxe2x80x9d structure by using laminations of various metals to form multilayered metal stack. Subsequently, the lower lamination is etched selectively to form an undercut with respect to the upper laminations to create a xe2x80x9cT-Shapedxe2x80x9d structure. The preferred materials of the metallic laminations are Al, Ti, and Pt and the selective etch is performed using NaOH a chemistry. In one embodiment, the source and drain electrodes are formed by an angle deposition technique.
U.S. Pat. No. 6,284,613 of Subrahmanyam et al. entitled xe2x80x9cMethod for Forming a T-gate for Better Salicidationxe2x80x9d describes a complex method of forming a xe2x80x9cTxe2x80x9d gate structure by using a damascene technique in conjunction with an additional lithographic mask step. The method does not allow for improved gate activation.
U.S. Pat. No. 6,107,667 of An et al. entitled xe2x80x9cMOS Transistor with Low-k Spacer to Suppress Capacitive Coupling Between Gate and Source/Drain Extensionsxe2x80x9d describes a method for making a MOSFET, which includes establishing a void in a thick field oxide layer on a silicon substrate. Then sidewall spacers are formed adjacent to sidewalls of the void, exposed portions of a gate oxide layer at the bottom of the void are removed. Then a high-k gate insulator is formed at the base of the void and the remainder of the void is filled with a first portion of a gate electrode so that the high-k gate insulator is sandwiched between the gate electrode and the substrate. Next the spacers and the extension of a previously formed gate oxide layer are stripped away exposing the sidewalls of the initial gate electrode. A protective layer is formed on the sidewalls of the initial gate electrode and the now exposed walls of the void. Then the space remaining within the void is filled with, a low-k gate spacer inside the protective layer. Then a conductive cap is formed over the initial gate and the gate spacer (completing a T-shaped gate) The conductive cap extends directly above the source and drain extensions of the MOSFET. In summary, the An patent teaches a method of fabricating low-k dielectric constant spacers by using a replacement gate technique. The low-k spacers are recessed and a xe2x80x9cTxe2x80x9d shaped gate is formed by a deposition and etch back procedure. The invention does not teach a method of simultaneously improving gate activation, extension resistance, and decoupled source drain silicidation from gate silicidation.
U.S. Pat. No. 6,239,007 Wu entitled xe2x80x9cMethod of Forming T-Shaped Gatexe2x80x9d describes a method of forming a T-shaped gate by sequentially forming a first conformal insulation layer over an initial gate structure and then forming a second insulation layer thereover, with the first insulation layer having a faster etching rate for a given etchant. Planarization of the second insulation layer exposes part of the first insulation layer by etching with the given etchant to remove the first insulation layer sufficiently to expose the top of the initial gate structure. A conductive layer is then formed over the exposed gate structure and planarized out so that only the portion of conductive layer above the gate structure remains. The insulation layers are removed using the conductive layer above the gate structure as an etching mask leaving spacers alongside the initial gate structure. A silicide process is carried out to form a silicide layer over the conductive layer and over the semiconductor substrate, but neither a source region nor a drain region is shown. Wu teaches a method of forming a xe2x80x9cTxe2x80x9d gate structure by depositing a conformal film on top of a patterned gate stack. A dielectric material is deposited and planarized to the top of the covered gate. The conformal film is removed and a conductive material is deposited and planarized to form the xe2x80x9cTxe2x80x9d structure. This invention does not teach a method of simultaneously improving gate activation, extension resistance, and decoupled source drain silicidation from gate silicidation as our invention does.
U.S. Pat. No. 6,159,781 of Pan et al. entitled xe2x80x9cWay to Fabricate the Self-Aligned T-Shape Gate to Reduce Gate Resistivityxe2x80x9d describes a method of fabricating a semiconductor field effect transistor, wherein the gate has a short foot portion in contact with the semiconductor substrate for a short gate length and consequent low capacitance, and a large amount of metal in a contact portion for low gate resistance. Salicides are formed on the T-gate source on drain contact areas resulting in large, low resistance contact areas. Trench insulation regions are formed within a semiconductor substrate. A blanket dielectric layer is deposited over the device and then a first trench is etched within the dielectric layer leaving a dielectric depth of deposition between the bottom of the trench and the substrate which equals the height of the foot of the T-gate. Sidewall spacers are formed against the walls of the first trench. A second trench is etched through the bottom of the first trench down to surface of the substrate. A second trench centered within the first trench is formed which is equal to the width of the foot of the T-gate. The sidewall spacers are removed and a conductive layer is formed over the structure formed by the dielectric layer, filling both the first trench and the second trench. Then the conductive layer is planarized by CMP down to the level of the top of the dielectric layer. Then the dielectric layer is etched down to the level of the top of the surrounding trench insulation regions along the left hand side of the left wall of the first trench and the right hand side of the right wall of the first trench further using the downward extensions of the left and right wall of the first trench as the line along which the etching process is extended in a downward direction. Source and drain regions are formed in the substrate and on the immediate inside or T-gate side of the surrounding trench insulation regions. Large angle lightly doped depositions are formed on the T-gate side of the sources and drains. Salicide is formed across the top of the T-gate structure and the top of the source/drain regions. In summary the Pan et al. patent teaches a method of forming a xe2x80x9cTxe2x80x9d gate structure by patterning and etching a trench in a dielectric material, sidewall spacers are next fabricated and used to etch a smaller trench in the dielectric. The method in this invention is quite different from ours and to add to this, the invention does not teach a method of simultaneously improving gate activation, extension resistance, and decoupled source drain silicidation from gate silicidation as our invention does.
U.S. Pat. No. 5,559,049 of Cho for xe2x80x9cMethod of Manufacturing a Semiconductor Devicexe2x80x9d describes forming a semiconductor by forming a gate electrode in the form of T-shape and forming auxiliary gates which are capacitively coupling with the T-shape gate electrode at undercut portions below both sides of T-shape gate. A lightly doped region is formed in the silicon substrate below the auxiliary gate by utilizing a doped oxide film, and forming a heavily doped region connected to a lightly doped region. A short channel length is provided. Auxiliary gates float electrically against the lightly doped extension to reduce the extension resistance. The xe2x80x9cTxe2x80x9d shape is created by using a multiple layer gate material with the lower layer etched selectively to the upper layer. The structure and method of Cho are very different from the present invention which utilizes a self aligned method to form the xe2x80x9cTxe2x80x9d gate structure. Cho does not teach a method to simultaneously improve gate activation by decoupling source drain and gate implantation steps, reduce extension resistance by angled and normal incidence extension implants, and decoupled source drain silicidation from gate silicidation steps.
U.S. Pat. No. 6,270,929 of Lyons, et al. entitled xe2x80x9cDamascene T-Gate Using a Relacs Flowxe2x80x9d describes a method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer covered with a gate oxide layer below a polysilicon layer covered in turn by an insulating layer. A photoresist layer is formed over the insulating layer with an opening therethrough extending partially into the insulating layer from a top surface thereof to a first depth. The photoresist layer is swelled to reduce the size of the opening in the photoresist layer. The opening is then extended in the insulating layer from the first depth to a second depth. The opening is wider from the top surface of the insulating layer to the first depth than the opening is from the first depth to the second depth. The opening is then filled with a conductive material to form a T-gate structure. Lyons et al uses a resist reflow technique to create the xe2x80x9cTxe2x80x9d structure. First, a resist pattern is used to etch a trench in a dielectric material. Next, the resist is swelled so that the resist pattern becomes narrow compared to the original pattern. Then, a second trench with smaller dimensions is etched into the dielectric. The structure is then filled to form the xe2x80x9cTxe2x80x9d. The method of Lyons et al is very different from the present invention in that it does not teach a method to simultaneously improve gate activation by decoupling source/drain and gate implantation steps, reduce extension resistance by angled and normal incidence extension implants, and decoupled source drain silicidation from gate silicidation steps as our invention does. No description of how to form extensions or source or drain regions is included in Lyons et al.
U.S. Pat. No. 6,309,933 Li, et al. entitled xe2x80x9cMethod of Fabricating T-Shaped Recessed Polysilicon Gate Transistorsxe2x80x9d describes a method of fabricating a semiconductor transistor device. A pad layer is formed over an upper silicon layer, and a well is implanted within the upper silicon layer. A lower SiN layer is deposited and patterned over the pad dielectric layer to define a lower gate area. The pad dielectric layer and the upper silicon layer within the lower gate area are etched to form a lower gate trench. A sacrificial liner oxide layer is formed in the trench followed by a threshold implant followed by a punchthrough implant into the upper silicon layer through the liner oxide layer. A lower gate portion is formed within the lower gate trench. An upper oxide layer is formed over the lower SiN layer. An upper SiN layer is formed over the upper oxide layer. The upper SiN layer is etched to define an upper gate trench having a predetermined width greater than the lower gate trench predetermined width. An upper gate portion is formed within the upper gate trench, wherein the lower and upper gate portions form a T-shaped gate. The etched upper SiN, upper oxide, and lower SiN layers are removed to expose the T-shaped gate extending above the pad dielectric layer. An uppermost oxide layer is formed over the exposed T-shaped gate. LDD regions are formed adjacent to the gate with an angled ion implantation. SiN sidewall spacers are formed adjacent the exposed vertical side walls of the lower polysilicon gate portion. S/D ion implantation is made forming S/D regions 800xc3x85 to 1000xc3x85 below the surface of the substrate. Silicide regions are formed over the T-shaped gate and source/drain regions.
U.S. Pat. No. 6,326,290 Chiu entitled xe2x80x9cLow Resistance Self Aligned Extended Gate Structure Utilizing a T or Y Shaped Gate Structure for High Performance Deep Submicron FETxe2x80x9d describes forming a low resistance self aligned salicided T-shaped FET gate structure. A gate oxide layer formed on a substrate active area is covered with a first poly gate electrode layer. Those layers are patterned into a gate electrode stack followed by implanting S/D lightly doped extensions. Oxide sidewall spacers are formed, Deep region dopant is implanted to form S/D regions. Then a very thick layer of a conformal covering oxide is formed over the device covering the gate electrode stack and the active device surface, planarized to a level above the stack and selectively etched to expose the top of the first poly gate electrode. The first poly electrode is selectively etched to recess it within the covering oxide layer. Then isotropic etching of the covering oxide opens a depression therein around the top of the first poly electrode. A second layer of poly is deposited and planarized over the active device area leaving the second poly remaining only in the depression on top of the first poly electrode and within the oxide covering layer forming a T shaped top of the gate electrode. Selective dry etching follows removing the covering oxide layer except for oxide sidewalls spacers remaining on the vertical sides of the first poly electrode between the active device surface and the second poly T shaped top thereby forming gate spacer oxide isolation. Then salicide is formed over the top surfaces of the second poly T shaped element and the device active area.
An object of this invention is a method providing an FET device that has improved gate activation, line resistance, and S/D extension resistance.
Another object of this invention is to provide a method of decoupling the gate from source drain ion implantation, thereby, achieving a highly activated gate with no degradation to short channel behavior. Improved gate activation is a very attractive feature of this device since polysilicon depletion is a major concern of advanced high performance CMOS.
Still another object of this invention is to provide a method for providing enhanced line resistance without compromising minimum polysilicon line width or Across Chip Linewidth Variation (ACLV).
In accordance with this invention, a method is provided for fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed, over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Optionally, form a silicide on the exposed portion of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate. Form silicide layers on the source/drain regions.
In accordance with the method of this invention a self-aligned widening technique forms a xe2x80x9cTxe2x80x9d structure which allows for increased area to form silicide. Current data shows that it is difficult to form CoSi2 on lines that are 60 nm and below in width. Thus, the feature of increasing the top portion is critical to high performance logic applications.
In accordance with this invention source/drain extension characteristics are improved by utilizing the T structure to perform multiple angle ion implants without additional lithography steps. This allows the NFET extension to have an angled as well as a normal incidence ion implant to reduce extension resistance. The method also allows for the PFET to be implanted at a normal incidence so that the xe2x80x9cTxe2x80x9d structure blocks the ion implant to create an offset for the as implanted PFET extension. The advantage here is that no PFET spacer is required. Specifically, the fact that there is no need for a PFET spacer overcomes problems associated with arsenic (As) dose loss, since it has been found that the PFET spacer processing causes a severe dose loss for the NFET extension.
Still further in accordance with this invention, a self-aligned method is provide for independently forming silicide on the gate electrode compared to the source drain. This is a highly desirable feature for thin silicon SOI applications, since it allows a thicker silicide to be formed on the gate and a thinner silicide to be formed on the source drain region. This is critical because the external resistance of the device increases if the source drain Si becomes completely silicided while the gate resistance is reduced and overall silicide yield improves with increased silicide thickness.
Preferably recess the lower gate structure to form a recessed lower gate within the planarizing layer before forming the upper gate; etch the planarizing layer to define a wide recess therein having a width greater than the width of the lower gate electrode structure; and then form the upper gate within the wide recess on the recessed lower gate whereby the lower gate electrode structure and upper gate structure form the T-shaped gate electrode.
Alternatively, it is preferred to partially recess the planarizing layer below the level of the lower gate top before forming the upper gate; then selectively grow the upper gate on exposed surfaces of the lower gate top to form the T-shaped gate electrode.
Another alternative is to recess the lower gate structure to form a recessed lower gate within the planarizing layer before forming the upper gate; then grow the upper gate on the surface of the lower gate within the recess and overgrow the upper gate above the planarizing layer whereby the lower gate electrode structure and upper gate structure form the T-shaped gate electrode.
Another alternative is to perform a silicidation to the exposed portion of the gate stack.
Preferably form the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode; form the NFET extensions by a combination of a vertical angle ion implant of arsenic ions and a tilted angle ion implant of arsenic ions, and form the PFET extensions by only a vertical angle ion implant of boron ions.
It is further preferred to form the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode, form the NFET extensions by a combination of a vertical angle ion implant of dopant ions and a tilted angle ion implant of dopant ions, and form the PFET extensions by a vertical angle ion implant of dopant ions.